As feature size of transistors is scaled down, it is not only the size of electrodes (source, drain, and gate) that become smaller, but also the distance between the electrodes that becomes smaller. The close proximity of adjacent electrodes increases the electric field between the electrodes during operation. For overall integrated circuit performance, it is desirable to minimize parasitic capacitance, while maximizing drive currents without increasing the off-state leakage of the device.
The height of gate structures effects the parasitic capacitance between the gate and the source and drain (S/D) contact structure, as well as the extension doping regions that overlap with the gate and S/D contact structure. The reduction of gate height decreases the peripheral components of outer-fringe capacitance between the gate line and the source/drain electrodes.
However, complementary metal oxide semiconductor (CMOS) processing with self-aligned source/drain/gate implantation limits the amount by which the gate height can be reduced, since implanting dopants using gate structures as a mask to provide the source/drain and halo regions of the device can cause the dopants to penetrate through the gate structures into the channel. Therefore, as the gate height is decreased, the risk of a gate impurity contaminating the underlying gate dielectric increases.